Experimental Study on Cell-Base High-Performance Datapath Design

نویسندگان

  • Masanori Hashimoto
  • Yashiteru Hayashi
  • Hidetoshi Onodera
چکیده

This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistorlevel circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35μm technology. From the experimental results, we can scarcely observe that manual cell placement contributes to improve circuit performance. On the other hand, transistor-level circuit optimization is so effective that circuit delay is reduced by 11–20% and power dissipation decreases to 42–62%. We can see that, in the case of cell-base design, transistor-level optimization is also important as well as in the case of custom design, whereas cell-base bit-slice layout has less importance to circuit performance. key words: datapath design, bit-slice layout, transistor sizing, cell-base design

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تاریخ انتشار 2002